Design Service
Design Service

In recent years, the increasing complexity and functionality of SSD controller have resulted in much more challenges than traditional implementations for the SoC designers to equip with expertise in IP development, IP integration, verification, architecture partition between hardware and software, and system architecture to ensure high SSD quality.

In EpoStar, we have a cohesive engineering team working together for many years. The team is highly experienced in SoC design and has been through several production tape-outs. We provide different services including IP development and customization, ASIC design service, SSD controller NRE and joint development, SSD ODM, etc. With our capabilities and experiences, we can help customers have great success in the SSD markets.

AISC Design Capabilities
+Tens of millions gates Large scale design experiences
+Key IP development

     NVMe, ECC, flash control, buffer management, bus fabrics, etc.
+IP handling
     CPU:ARM, Tensilica, ARC, Andes, etc.
     PCIe core and PHY:PLDA, Semtech, GUC, Phison, etc.
     DDR controller and PHY:Synopsys, GUC, Phison, Cadence, etc.
     Bus fabrics:Arteris, Synopsys, GUC, etc.
+Design flow
     Low power, power sim, synthesis, STA, formal, Lint, CDC, DFT, ECO
+FPGA implementation and validation
Design Verification Capabilities
+Advanced UVM methodology
     Supported by major simulators
     From IPs to Subsystems to Whole Chip
+Coverage driven flow
     Cross check code coverage with functional coverage
+Constrained Random Test and Direct Test pattern
+White-Box Error Injection
+Third Party Verification-IP Integration Environment
+Reusable Sub-block Monitor Components
+Easy to switch Define/Memory-Map/Reference Firmware in an Unique Flexible Environment
Firmware Development Capabilities
+Enterprise PCIe-NVMe SSD FW development
     Data integrity, IO-throttling, performance consistency
+Client PCIe-NVMe SSD FW development
     Power armor, power throttling, power mode handling
+PCIe/NVMe, SATA, eMMC/UFS host interface
     IO command scheduling, compliant and compatibility
+ONFI/Toggle, eMLC/cMLC/TLC/3D NAND flash
     Retention/endurance, profiling,
+NAND flash and error reduction algorithm
+Multiple processor programming
+Good user experience benchmarking
+Design flow from FW/ASIC architecture, FPGA validation, reference FW, to mass-production